1. Field of Invention
The present invention is related to a semiconductor device and its method of fabrication, especially is related to a method of fabrication of a metal oxide semiconductor field effect transistor having strained layer.
2. Description of Related Art
The semiconductor industry and wafer fabrication is headed towards higher efficiency and ultra large-scale integration. For the sake of accomplishing higher effectiveness using the same amount of footprint area, the wafer characteristic dimensions and supply voltage will continue to diminish. Generally speaking, if other characteristics are held constant, the power consumption of each device will increase according to the on/off frequency. Therefore, although the supply voltage and the capacitance load is decreased, the power consumption of the wafer is gradually increasing. Furthermore, when the dimensions of the field effect transistor have become smaller, the commonly known short channel effect will become more pronounced, thus contributing to the severity of the power consumption issue.
The method for improving short channel effect includes the disposition of the source and the shallow source/drain extensions. Using fabrication of the metal oxide semiconductor field effect transistor as an example, an implantation of ions is performed within an elongated region of high dosage first through a mask after the gate is established, and at the two side walls of the channel to form shallow extensions. Later, a spacer is formed at the side wall of the gate, and a source/drain layer is formed in the substrate outside of the spacer. Followed by an annealing procedure is later performed. Annealing to activate the doping ion is then performed, and the shallow extending internally dopant is allowed to diffuse towards the channel region. Although the dopant diffused towards the channel region can improve, for example, punch through and other issues, the dopant diffusion rate is difficult to control, and excessive dopant will damage the transistor efficiency.
Furthermore, for improving further on the short channel effect, conventional technology is using halo implant to inhibit the so-called punch through effect. However, the ion for the halo implant will decrease the drain current, and based on the fact of continuous gate dimensional shrinkage, this issue will become more pronounced, thus disallowing the transistor efficiency to further improve.